CV

Shenzhen, China

B.Eng. in Electronic Engineering

GPA 3.61 / 4.0 (3.92 this academic year)

New York, USA

Exchange Program (Electrical Engineering)

GPA 4.0 / 4.0

Student Researcher，Supervised by Dr. Abraham Vazquez　North Carolina State University

• Built a resumable incremental uploader: it sends data while recording is still going, and only the newline-terminated bytes the server has not yet acknowledged. Each file carries its own acknowledged byte offset, so a reconnect resumes from that byte instead of resending the file.
• A partial final row is never sent. It sounds like a detail, but without it the server receives half a record mid-session — and downstream analysis cannot tell a genuinely short row from an unfinished one.
• A retry sends the identical byte range and SHA-256. The server rejects gaps and treats an identical retry as a duplicate, which makes retrying safe by construction rather than by luck.
• Uploads are woken by native filesystem events (FSEvents on macOS, inotify on Linux/Jetson) rather than polling — polling is either slow or power-hungry, and an acquisition rig can afford neither.
• Completion is explicit: End Session and Quit writes a SHA-256 sidecar. Idle time is never treated as proof that acquisition has ended — to a filesystem, a subject taking a break and a finished experiment look identical.
• Implemented accounts on the server with FastAPI and SQLAlchemy: data belongs to a person, and an administrator can retrieve it by user, by session, or by individual file. Deletion moves items to a trash with a retention countdown shown in the interface, rather than destroying them outright.
• Added an activity log covering sign-ins, sign-outs, permission changes and upload batches, so an administrator can see who is online and who has recently uploaded.
• Wrote a screenshot-by-screenshot manual for non-programmers. Not everyone who records data in the lab writes code — a system nobody can operate is no system at all.

Visiting Student Researcher，Supervised by Dr. Yuchen Liu　North Carolina State University

• Built and maintained a Crazyflie-based multi-drone testbed with indoor localization using the Loco positioning system.
• Developed Python-based control and logging pipelines using crazyflie-lib-python for real-time multi-drone coordination and data collection.
• Conducted experiments on multi-agent reinforcement learning and swarm control in both simulation and physical drone environments.

Visiting Student Researcher，Supervised by Dr. Shan Lin　Stony Brook University

• Designed and implemented a wireless system for synchronous acquisition of finger- and wrist-based PPG signals, enabling time-aligned multi-channel data transmission.
• The first build ran on an ESP8266, but the link was unstable enough that measurements still depended on cables — a wireless rig that left the subject tethered, which defeats the point. Moving to the ESP32 with the ESP-NOW protocol cut latency and held the link steady; only then could subjects move freely, which is the precondition for the whole study.
• Incorporated motion event detection to identify motion-induced artifacts and support robust signal segmentation under dynamic conditions.
• Improved the device's efficiency and stability in practical applications through wireless communication technology and low-power design.
• Integrated signal processing features with machine learning models to analyze cross-channel similarity and improve the robustness of identity consistency assessment.
• Extended the system architecture to support additional sensing channels and ongoing refinement of signal processing methods for operation under motion and environmental variability.

Research Assistant　Key Laboratory of Quantitative Remote Sensing, Ministry of Agriculture and Rural Affairs; Information Technology Research Center, Beijing Academy of Agriculture and Forestry Sciences

• Processed multi-temporal remote sensing imagery data from drones.
• Employed machine learning methods such as SHapley Additive exPlanations (SHAP) and Particle Swarm Optimization (PSO) for feature selection.
• Assisted in optimizing ensemble learning models, leveraging the PSO algorithm to enhance the models' predictive capabilities and multi-stage generalization performance.
• Identified key features correlated with the chlorophyll content of rice paddies.

Course Project · Innovative Experiments in Electronic Science III，Supervised by Dr. Junmin Jiang　SUSTech

• Built live preview and capture on Picamera2, with a seven-page PySide6 desktop UI: home, capture, story, prompt, video, history and settings.
• Designed three creative modes: shoot reality (photo + story), recover a dream (text or voice), and black-box finale (reconstruction from narrative fragments).
• Used OpenAI Chat Completions as an "AI director" to turn photo and story into a cinematic treatment, then compressed and translated it into short English Runway prompts via a dedicated optimizer.
• Added real-time speech-to-text over the OpenAI Realtime WebSocket, with a volume gate, auto-submit on silence, a maximum segment length and retained recordings — fixing unstable transcript segmentation.
• Drove the Runway API for generation across Gen-4 / Gen-4.5 / Veo / Seedance model configurations, running jobs on a background thread so a multi-minute wait never froze the UI.
• Unified photos, text, audio, prompts and videos into session directories (metadata.json plus photos/story/prompts/videos/audio) so every piece stays traceable.
• Modelled and 3D-printed a three-part enclosure: a front window for the camera module, side cutouts for power and Ethernet, designed around ribbon-cable bend radius and serviceability.

Course Project · Team of four (my share: 25%)，Supervised by Dr. Fei Chen　SUSTech

• I owned the overall code architecture, the audio file management layer, and the demo; MFCC extraction, preprocessing and GMM training were handled by my three teammates.
• Routed training and recognition through one shared feature-extraction entry point, so the training set, test set and live recordings all pass through an identical preprocessing chain — a mismatch there is the most easily missed source of error in this kind of system.
• Preprocessing chain: mono downmix, DC removal, amplitude normalization, resampling to 8 kHz, an 80–3400 Hz bandpass, and endpoint detection driven by short-time energy and zero-crossing rate.
• Features are MFCCs with CMVN normalization, which suppresses the channel differences introduced by different microphones and recording levels.
• Modelling uses a 16-component GMM per speaker, trained with EM.
• The decision layer applies two thresholds — a stranger threshold (top score below it means unknown) and a score-margin threshold (first and second too close means uncertain) — yielding confirmed / uncertain / stranger.

Course Project · Team of two　SUSTech

• The transmitter was written in class; our work was the receiver — swapping the queued input for real USRP drivers to close the hardware loop.
• Text is mapped to bits via Unicode, split into blocks, and wrapped with guard bits, a sync sequence, a packet number and a data field.
• Built the receive chain in LabVIEW: USRP session setup and configuration, IQ acquisition, resampling and PSK demodulation.
• Implemented frame synchronisation — searching the demodulated bit stream for the agreed sync sequence to locate packet starts, validating structure, then reassembling text by packet number.
• Used constellation and eye diagrams to judge signal quality in the phase and time domains respectively.
• Extended the modulation order from BPSK through QPSK and 8PSK to 16PSK, comparing demodulation behaviour at each.

Course Project，Supervised by Dr. Guang Wu　SUSTech

• Generated QPSK, 8-PSK, and 64-QAM baseband signals in MATLAB, including symbol mapping, upsampling, and square-root raised cosine (RRC) pulse shaping.
• Analyzed time-domain and frequency-domain characteristics of modulated signals using FFT to study bandwidth and spectral properties.
• Applied a convolutional neural network (CNN) to classify digital modulation schemes and interpreted classification probabilities.

Visiting Student (Course-based Design Project)，Supervised by Dr. Kenneth Short　Stony Brook University

• Designed and verified combinational and sequential digital circuits using VHDL, including AOI logic and addressable latch structures.
• Developed self-checking testbenches in Active-HDL to support functional verification of combinational designs.
• Implemented modular, parameterized VHDL components and reusable test/constraint templates to support scalable system design.
• Applied structured design methodologies to control a precision analog front-end (TC514) using FPGA-based logic.
• Worked through the full PLD design flow: selecting Lattice devices, writing timing and I/O constraint files, running synthesis and place-and-route in ispLEVER, analysing critical paths, and closing with SDF back-annotated post-implementation simulation in Active-HDL to verify setup and hold times.
• Three things actually stalled the project: timing simulations that would not pass, glitches on the asynchronous reset, and a race caused by a combinational feedback loop. Each was resolved through design changes, constraint tuning and simulation debugging — and together they are where I really understood why hardware has to be proven correct before it is committed.

Course Project · Team of four，Supervised by Dr. Guang Wu　SUSTech

• Measured the chip with calipers — 22 pins per side, 28 mm long — giving a 1.27 mm pitch; chose 2.54 mm headers to suit the ELVIS breadboard, with 61 mm between rows.
• Drew the schematic and PCB in LCEDA, fanning all 44 chip pins out to two 22-pin headers, and sent it out for fabrication.
• Soldered three different ways: spot soldering for the 2.54 mm headers, solder paste and hot air for the 1.27 mm chip pins, and hand soldering from both ends inward for the ribbon cable, whose insulation will not survive sustained heat.
• Traced faults pin by pin on NI ELVIS: resistance mode to find bridges between adjacent pins, continuity mode to find cold joints between pad and pin.
• When one console powered up dark, swapping the display changed nothing; testing showed an indicator LED lit regardless of whether the chip was present, which located the fault in the motherboard rather than the chip.

Course Project，Supervised by Dr. Seungwoo Je　SUSTech

• Designed the bodywork against a single hard constraint — the fixed chassis dimensions — with the styling otherwise unconstrained.
• Modelled the part and its assembly relationships in Fusion 360.
• Produced fully dimensioned engineering drawings.
• Rendered the design to evaluate the form.
• Sliced and printed, then checked key dimensions and chassis fit against the physical part.

Course-related Internship

• Participated in product development sessions and provided suggestions for feature optimization and improvements.
• Designed and demonstrated a new feature using an interface design tool.
• Conducted interviews at users' homes to identify product feature gaps and gather user feedback.