Digital Design Using VHDL and PLDs

Why this matters

Hardware is not software — once a chip is fabricated you cannot patch it. So the discipline is not just writing the circuit, it is being able to demonstrate that the circuit is right before it ships.

What I did

• Designed and verified combinational and sequential digital circuits using VHDL, including AOI logic and addressable latch structures.
• Developed self-checking testbenches in Active-HDL to support functional verification of combinational designs.
• Implemented modular, parameterized VHDL components and reusable test/constraint templates to support scalable system design.
• Applied structured design methodologies to control a precision analog front-end (TC514) using FPGA-based logic.
• Worked through the full PLD design flow: selecting Lattice devices, writing timing and I/O constraint files, running synthesis and place-and-route in ispLEVER, analysing critical paths, and closing with SDF back-annotated post-implementation simulation in Active-HDL to verify setup and hold times.
• Three things actually stalled the project: timing simulations that would not pass, glitches on the asynchronous reset, and a race caused by a combinational feedback loop. Each was resolved through design changes, constraint tuning and simulation debugging — and together they are where I really understood why hardware has to be proven correct before it is committed.

Technologies

• VHDL
• FPGA
• Active-HDL
• Self-Checking Testbenches
• Sequential Logic Design